The present invention relates to a MOS field plate trench transistor device (also called “MOS transistor device” for short hereinafter). As is known, a field plate trench is understood to be a trench with a thin gate oxide and a gate electrode in the upper region of the trench and a thick field oxide and a field plate in the lower region of the trench.
In modern MOS transistors, particularly in the power semiconductor sector, the area-specific on resistance Ron·A is an essential criterion in assessing the function of the respective MOS transistor.
The further development of modern transistor technologies often aims to reduce the area-specific on resistance Ron·A, so that, on the one hand, the static power loss can be minimized and, on the other hand, greater current densities can be achieved, which can result in the possibility of miniaturization of the chips in conjunction with cost-effective production.
Known measures for reducing the on resistivity of MOS transistors use trench cells instead of a planar cell structure, in which trench cells the MOS transistor is formed in the region of a trench structure that accommodates the gate electrode and the gate connection. As a result of this measure, the channel resistance, in particular, is reduced as a result of the increase in the channel width. Furthermore, the resistance of the drift path can be reduced further by using deep trench structures. Specific doping measures reduce the drift path resistance further.
For these and other reasons, there is a need for the present invention.